Background Art
As is well known, many applications related to semiconductor integrated electronic circuits require the use or generation of higher voltages than a supply voltage Vcc. In particular, electrically programmable non-volatile memories, such as EPROMs, EEPROMs, or FLASH EEPROMs, need a write voltage far above the standard 3 to 5 Volts supply.
The most up-to-date integrated circuit applications concern systems which utilize supply voltages in the 3-Volt range. Such systems often employ semiconductor memories of the non-volatile type. In order to maintain the characteristics of such active integrated devices as transistors or memory cells unchanged at low supply voltages, it has been necessary to introduce thin (160.ANG. or less) oxides.
However, it is a well recognized fact that EPROMs, EEPROMs and FLASH EEPROMs all require high (12V) programming voltages that such thin oxides cannot withstand. Thus, the introduction of a second and thicker (e.g. 20 to 30 nm) oxide has become necessary for high voltage transistors. These programming voltages must, in the instance of EEPROMs and FLASH EEPROMs, be generated internally from the external supply voltage by means of suitable circuits, known as voltage multipliers or charge pumps and based on the use of capacitors, which must be capable of withstanding the high voltages involved in the final stages of the circuit.
These capacitors can be formed between the polycrystalline silicon and a diffusion provided in the substrate, using the high voltage oxide as a dielectric. However, they have certain disadvantages, as follows:
the diffusion which forms one of the capacitor electrodes is part of the standard processing flow for EEPROMs, but involves an additional masking step for FLASH EEPROM memories; and PA1 one of the capacitor electrodes is connected to the substrate via a diode, which introduces limitations on the supply polarities.
On the other hand, non-volatile memories of the EPROM, FLASH EEPROM and EEPROM types include two levels of polycrystalline silicon, separated by a dielectric, which lend themselves ideally for forming a capacitor with both electrodes floating.
A limiting factor to the use, in integrated circuits of this kind, of capacitors formed between two levels of polysilicon is represented by the maximum voltage that the interpoly oxide can withstand. This oxide is usually quite thin (within the range of 15 to 20 nm), since it has to be used in memory cells. In fact, the efficiency of the memory cell is critically dependent on the coupling coefficient between the control gate and the floating gate, which is the better the thinner the interpoly dielectric, whose lower limit is only set by problems of faulty construction. However, forming thick and thin interpoly dielectrics simultaneously in the same device is a fairly complicated operation involving at least one masking step.
The underlying technical problem of this invention is to enable the formation of a high voltage capacitor in a double polysilicon level, monolithically integratable on a semiconductor substrate without the addition of technological steps to the manufacturing process of the device to which the capacitor is integrated, thereby overcoming the aforementioned limitations of the prior art.
The technical problem is solved by a capacitor as further described below.